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Jobs/San Francisco/Design Verification Engineer
San Francisco, CA

Design Verification Engineer

About the Team: OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integ

Company
OpenAI
Compensation
$226K - $445K
Schedule
Full-Time
Role overview

What this role actually needs.

About the Team: OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integ Responsibilities: - Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality. - Define verification plans based on architecture and microarchitecture specs. - Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies. - Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness. - Drive bug triage, root cause analysis, and work closely with design teams on resolution. - Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments. Company context: OpenAI builds frontier AI systems, research infrastructure, and applied products for developers, enterprises, and global users.

Responsibilities

Day-to-day expectations

OpenAI lists these responsibilities for the Design Verification Engineer role.

  • Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality.
  • Define verification plans based on architecture and microarchitecture specs.
  • Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.
  • Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.
  • Drive bug triage, root cause analysis, and work closely with design teams on resolution.
  • Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments.
UpJobz market context

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United States tech market

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Compensation read

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Work authorization read

Current extracted signal: United States residents. UpJobz treats this as a search signal, not legal advice, and links visa-sensitive roles back to the relevant visa hub where possible.

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Interview themes

Artificial IntelligenceHybridaillmmachine-learningresearch

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aillmmachine-learningresearchawssecurityapipythoninfrastructure
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Source: jobs.ashbyhq.com · Source ID: 3a415c1d-4f66-4578-8eb3-8b15ef0ab52b · Confidence: 97/100 · Last checked: May 7, 2026

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