Hardware Tools Engineer
About the Team OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integr
What this role actually needs.
About the Team OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integr Responsibilities: - Build and improve the software tooling that makes hardware teams faster: compilation, IR transforms, RTL generation, simulation, debug, and automation. - Extend and integrate hardware compiler stacks (frontends, IR passes, lowering, scheduling, codegen to Verilog/SystemVerilog) and connect them to real design workflows. - Improve developer experience and reliability: reproducible builds, better error messages, faster iteration loops, and dependable CI and regression infrastructure. - Work closely with designers and verification engineers to turn real pain points into durable tools. - Dive into RTL when needed: read and reason about Verilog/SystemVerilog to debug issues, validate tool output, and improve debuggability. - Be willing to go all the way down the stack when necessary, including gate-level views, synthesis results, and implementation artifacts. Company context: OpenAI builds frontier AI systems, research infrastructure, and applied products for developers, enterprises, and global users.
Day-to-day expectations
OpenAI lists these responsibilities for the Hardware Tools Engineer role.
- Build and improve the software tooling that makes hardware teams faster: compilation, IR transforms, RTL generation, simulation, debug, and automation.
- Extend and integrate hardware compiler stacks (frontends, IR passes, lowering, scheduling, codegen to Verilog/SystemVerilog) and connect them to real design workflows.
- Improve developer experience and reliability: reproducible builds, better error messages, faster iteration loops, and dependable CI and regression infrastructure.
- Work closely with designers and verification engineers to turn real pain points into durable tools.
- Dive into RTL when needed: read and reason about Verilog/SystemVerilog to debug issues, validate tool output, and improve debuggability.
- Be willing to go all the way down the stack when necessary, including gate-level views, synthesis results, and implementation artifacts.
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Source: jobs.ashbyhq.com · Source ID: 467cbfac-3e7d-4cc6-a131-2b26617afa02 · Confidence: 97/100 · Last checked: May 7, 2026
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